Title :
Optimized VLSI design for enhanced image downscaler
Author :
Lee, Honam ; Lee, Bonggeun ; Lee, Youngho ; Kang, Bongsoon
Author_Institution :
Sch. of Electr., Electron., & Comput. Eng., Dong-A Univ., Pusan, South Korea
Abstract :
Proposes the optimized hardware architecture for a high performance image downscaler. The proposed downscaler uses nonlinear digital filters for horizontal and vertical scalings. In order to achieve the optimization the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two´s power. The usefulness of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using VHDL and implemented by using the IDEC-C632 0.65 μm cell library
Keywords :
VLSI; circuit optimisation; digital filters; hardware description languages; image enhancement; integrated circuit design; nonlinear filters; 0.65 micron; IDEC-C632; VHDL; cell library; filter coefficients; horizontal scaling; image downscaler; multiplexer-adder type scheme; nonlinear digital filters; optimized VLSI design; vertical scaling; Clocks; Computer architecture; Delay effects; Design optimization; Digital filters; Electronic mail; Hardware; High performance computing; Pixel; Very large scale integration;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896928
