A Σ-Δ modulator architecture reducing intermodulation of tones near fs/2 into the baseband

In a sampled system, a signal that is commonly present on chip that is particularly troublesome if coupled into the reference is a clock at frequency fs/2, where fs is the high-frequency sampling rate. The presence of a signal at frequency fs/2 on the reference will cause spectral components in the signal near fs/2 to mix down into the baseband. Especially in Σ-Δ modulator the output bit stream will contain large amounts of quantization noise at frequencies around fs/2 and the intermodulation should be minimized to the highest degree to avoid baseband destruction. In this paper a systematic way where a modulator transfer function is modified to reduce intermodulation effect is proposed. Simulations show the effectiveness of the method