Title :
Efficient 8-cycle DES implementation
Author_Institution :
Syst. IC R&D Div., Hyundau Electron. Ind. Co. Ltd., Seoul, South Korea
Abstract :
This paper describes an efficient DES implementation that encrypts a 64-bit plain text block in 8 clock cycles. The 8 cycle processing latency optimizes the throughput of a pipelined DES system, where a byte-wide bus is used. Also, by decreasing the system clock frequency by a factor of 2, the switching power consumption is reduced compared to the conventional implementations. Our approach is based on the time multiplexed cipher function that requires only one copy of S-Box realization unlike other 8-cycle implementations
Keywords :
cryptography; pipeline processing; time division multiplexing; 64 bit; S-Box realization; byte-wide bus; clock cycles; eight-cycle DES implementation; pipelined DES system; plain text block; processing latency; switching power consumption; system clock frequency; throughput; time multiplexed cipher function; Clocks; Computer architecture; Cryptography; Data security; Delay; Electronic mail; Electronics industry; Research and development; Scheduling; Throughput;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896937
