Title :
Designing built-in self-test circuits for embedded memories test
Author :
Park, Sanghun ; Lee, Kijong ; Im, Changbum ; Kwak, Nami ; Kim, Kihyun ; Choi, Youngdoo
Author_Institution :
Hyundai Electron. Ind. Co. Ltd., Seoul, South Korea
Abstract :
This paper describes practical issues on designing and implementing industrial built-in self-test circuits for embedded memory test. The proposed test circuits are power conscious, fault locatable, and scan-based-test friendly. These features are notable and useful practically in system-on-a-chip design test because many memories that are repairable and large-sized are commonly embedded in the design. We applied the proposed test circuits to actual RAMs available in industry. Experimental results show that the test circuits are powerful for the RAM test with small penalties of area, delay, and power consumption, compared with no use of the test circuit. Furthermore, the test circuits improve the scan-based testability for the glue logic surrounding the RAMs
Keywords :
application specific integrated circuits; boundary scan testing; built-in self test; delays; fault diagnosis; integrated circuit testing; logic testing; random-access storage; RAMs; area; built-in self-test circuits; delay; embedded memories test; fault locatable; glue logic; power consumption; scan-based testability; scan-based-test; system-on-a-chip design test; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Delay; Logic testing; Random access memory; Read-write memory; System testing; System-on-a-chip;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896971
