New efficient hardware design methodology for modified non-restoring square root algorithm

This paper shows a new methodology to design the hardware for computing square root of N-bit unsigned numbers. The proposed hardware design is based on the modified non-restoring square root algorithm. Two different hardware designs, sequential pipeline architecture and asynchronous architecture for computing N-bit fixed point square root operation are proposed. The synthesis report of the designed FPGA based pipelined hardware for 32-bit square root operation shows that the usage of the logical resources of FPGA is significantly less than that of the earlier proposed pipelined hardware designs based on modified non-restoring algorithm. Moreover, the proposed pipelined hardware design can be configured to calculate square root of 32-bit number in 16 and 8 clock cycles. The maximum frequency achieved for the operation latency of 16-clock cycles for computing 32-bit unsigned square root is 403.770 MHz. The maximum frequency achieved for operating latency of 8-clock cycles is 260.233 MHz. On the other side, proposed asynchronous architecture based FPGA hardware design supersedes the earlier proposed asynchronous hardware designs for N-bit square root operation in terms of the less usage of hardware resources. Both the pipelined and asynchronous hardware designs are tested on Xilinx Virtex 7 XC7VX980T-2, Virtex 5 XC5VLX330T-2 and Spartan 3E XC3S1600E-5 FPGAs.