A novel algorithm for multi-node bridge analysis of large VLSI circuits

Author

Zachariah, Sujit T. ; Chakravarty, Sreejit

Author_Institution

Archit. Group, Intel Corp., Santa Clara, CA, USA

fYear

2001

fDate

2001

Firstpage

333

Lastpage

338

Abstract

Defects that short two or more modes are known as multinode bridges. Multinode bridge analysis can be used to extract a list of either only two-node bridges or multi-node bridges. We discuss why multi-node bridge analysis is also required even if only two-node bridges are targeted. We propose a novel, scalable and accurate algorithm for multinode bridge analysis of large layouts. CARAFE can perform multi-node analysis only on small layouts. Comparison results show that for small layouts our algorithm is considerably faster than CARAFE. For larger layouts experimental results are provided to illustrate the performance and capacity of our algorithm

Keywords

VLSI; circuit analysis computing; fault diagnosis; integrated circuit layout; integrated circuit testing; CARAFE; IC testing; large VLSI circuits; layouts; multi-node bridge analysis; Algorithm design and analysis; Bridge circuits; Circuit analysis; Circuit faults; Circuit testing; Computer aided manufacturing; Geometry; Performance analysis; Very large scale integration; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2001. Fourteenth International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

0-7695-0831-6

Type

conf

DOI

10.1109/ICVD.2001.902681

Filename

902681