Title :
Study on failure mode of solder bump fabricated using eutectic solder electroplating process
Author :
Xiao, Guo-Wei ; Chan, Philip C.H. ; Teng, Annette ; Cai, Jian ; Yuen, Matthew M F
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China
Abstract :
The electroplating-based flip chip process has many advantages over other solder bumping methods, where the bump fabrication process can affect the reliability of solder joints. In this paper, the effect of the UBM and electroplating process of the solder bump on the shear strength of the solder bump is studied, as well as the relationship between the shear test failure mode and solder bump fabrication process. It is reported that the Cu surface roughness is affected by the Cu plating current density and the appropriate current density is in a range from 10~40 mA/cm2. The solder bump plating process temperature should be within 30-35°C. It is observed that the growth kinetics of intermetallic compound formation are affected by the Cu stud structure. The ratio of Cu3Sn to the total Cu-Sn IMC layer thickness was from 0.5 to 0.15 with various Cu microstructures at 150°C during thermal aging tests. The activation energy was in the range of 0.78 eV to 1.14 eV. Five shear test failure modes are analyzed which are related to the electroplating process
Keywords :
ageing; current density; electroplating; eutectic alloys; failure analysis; flip-chip devices; integrated circuit interconnections; integrated circuit metallisation; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; interface structure; reaction kinetics; shear strength; soldering; surface topography; 0.78 to 1.14 eV; 150 C; 30 to 35 C; Cu microstructures; Cu plating current density; Cu stud structure; Cu surface roughness; Cu-Sn; Cu-Sn IMC layer thickness; Cu3Sn; Cu3Sn intermetallic; UBM; activation energy; bump fabrication process; current density; electroplating process; electroplating-based flip chip process; eutectic solder electroplating process; failure mode; intermetallic compound formation; intermetallic compound growth kinetics; shear test failure mode; shear test failure modes; solder bump fabrication; solder bump fabrication process; solder bump plating process temperature; solder bump shear strength; solder bumping methods; solder joint reliability; thermal aging tests; under-bump metallization; Current density; Fabrication; Flip chip; Intermetallic; Kinetic theory; Rough surfaces; Soldering; Surface roughness; Temperature; Testing;
Conference_Titel :
Electronic Materials and Packaging, 2000. (EMAP 2000). International Symposium on
Conference_Location :
Hong Kong
Print_ISBN :
0-7803-6654-9
DOI :
10.1109/EMAP.2000.904129
