DocumentCode
1742471
Title
Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)
Author
Lau, John H. ; Lee, S. W Ricky
Author_Institution
Agilent Technol., San Jose, CA, USA
fYear
2000
fDate
2000
Firstpage
115
Lastpage
126
Abstract
The creep analyses of solder-bumped wafer level chip scale packages (WLCSP) on build-up printed circuit boards (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the conventional PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and creep shear strain hysteresis loops, shear stress range, creep shear strain range, and creep strain energy density range at different locations in the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of the solder-bumped WLCSP on build-up PCB with microvia circuits. It is found that, due to the large coefficient of thermal expansion of the build-up resin, the effects of thickness of the conventional PCB with microvia build-up layer become much more significant than that without the microvia build-up layer
Keywords
assembling; chip scale packaging; circuit analysis computing; circuit reliability; creep; hysteresis; integrated circuit interconnections; lead alloys; printed circuit manufacture; reflow soldering; shear deformation; silver alloys; stress analysis; thermal expansion; tin alloys; Garofalo-Arrhenius steady-state creep constitutive law; PCB thickness; Sn-Ag-Pb solder joints; SnAgPb; WLCSP; WLCSP assembly; build-up PCB; build-up printed circuit board thickness; build-up resin; coefficient of thermal expansion; corner solder joint; creep analysis; creep shear strain hysteresis loop; creep shear strain range; creep strain energy density range; microvia build-up layer; microvia circuits; microvias; shear stress hysteresis loop; shear stress range; solder joint reliability; solder-bumped WLCSP; solder-bumped wafer level chip scale packages; thermal cyclic loading; thermal-mechanical behavior; wafer level CSP; wafer level chip scale package; Assembly; Capacitive sensors; Chip scale packaging; Creep; Printed circuits; Soldering; Steady-state; Thermal loading; Thermal stresses; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Materials and Packaging, 2000. (EMAP 2000). International Symposium on
Conference_Location
Hong Kong
Print_ISBN
0-7803-6654-9
Type
conf
DOI
10.1109/EMAP.2000.904141
Filename
904141
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