Chip scale packaging reliability

The introduction of underfill in flip chip packaging gave solder interconnect technology an unforeseen mechanical robustness and increased flip chip solder fatigue resistance. Derivatives from this technology (e.g. PBGA, CBGA, CSP, etc.) have been developed in recent years. New interconnect geometry is used extensively with moderate success in overcoming large mismatches in component displacements during temperature excursions and supports larger loading (e.g. heatsinks, etc.). However, environments and testing qualifications for these packages are becoming increasingly demanding. Failure mechanisms thought to have been eliminated, or at least alleviated to a manageable extent by new package designs, are again threatening integrity and reliability. Chip scale packages, first designed to eliminate the need for encapsulation, to be SMT process compatible, and to have good handling properties, etc., face serious reliability problems. High-power devices that require massive heatsinks could lead to cyclic creep phenomena due to the static load applied by these heat spreaders. Dynamic loading induced by mechanical vibration and impact shock results in reliability detractors for CSP and DCA packages. Analytical models and simulation of these mechanisms are proposed. This paper addresses failure mechanisms of CSP and DCA packages, and the effects and advantages of underfilling. We present and propose the encapsulation process as a natural and proven method to ensure reliable packages that overcome reliability threats. Models supporting encapsulation as a solution are presented. Data comparing encapsulated and nonencapsulated packages is also given