A low cost wafer level packaging process

Semiconductors are currently connected to other system components by three main interconnect technologies: wirebond, TAB and solder bump. These processes are significant contributors to the cost of the bumped wafer. In the packaging industry, there is also a drive for towards wafer level packaging solutions in order to minimize the packaging cost and give high production rates. This paper describes the development of a new wafer level process which minimizes the cost of the bumped wafer that requires bond pad redistribution, and at the same time offers the advantages of a wafer level packaging solution. The process is based on the concept of a build up technology that channels the bond pads to a large pitch array in order to make the interconnection to the board. The packaging technology is suited to high frequency, small size, lightweight applications. This process has the potential to drive the industry away from wire bonding to a single step wafer level interconnection process. The paper also provides the results of the characterization that was performed on the package