DocumentCode
1743158
Title
Advantages of wet chemical spin-processing for wafer thinning and packaging applications
Author
Hendrix, Mark ; Drew, Scott ; Hurd, Trace
Author_Institution
ST Microelectron., Carrollton, TX, USA
fYear
2000
fDate
2000
Firstpage
229
Lastpage
236
Abstract
Silicon thinning and stress relief are increasingly significant in the back end and assembly areas of semiconductor component manufacturing. The benefits of spin-processing technology with its accompanying aqueous chemical etchants can provide increased wafer and die strength, removal of surface damage, crystal defects and microcracks from backgrinding, and the ability to process wafers <100 μm in thickness using its Bernoulli handling system. ST Microelectronics experienced a 96.5% reduction in wafer breakage and scrap of backgrind material as a result of implementing spin-processing. It was confirmed that after wet chemical etching with an SEZ Spin-Processor 101, wafer warpage had decreased by 85%, wafer strength was up to 25 times stronger than with backgrind alone, and machine uptime was calculated at 99.4%. Using spin-processing for wafer thinning and strength enhancement also allows the user to control the surface finish. A smooth or rough surface can be achieved and wafers can be processed to these specifications while providing the same strength characteristics. As the roughened surface is created with chemicals, it does not introduce propagating crystalline defects, but leaves the wafer in an optimum state for back metal adhesion and contact resistance reduction. Similar results on highly doped wafers are easily obtained
Keywords
adhesion; contact resistance; crystal defects; deformation; etching; grinding; integrated circuit manufacture; integrated circuit packaging; internal stresses; materials handling; mechanical strength; microassembling; microcracks; stress relaxation; surface topography; 100 micron; Bernoulli handling system; SEZ Spin-Processor 101; Si; aqueous chemical etchants; assembly; back end processing; back metal adhesion; backgrind material scrap; backgrinding; contact resistance reduction; crystal defect removal; die strength; highly doped wafers; machine uptime; microcrack removal; optimum wafer state; packaging applications; propagating crystalline defects; rough surface; roughened surface; semiconductor component manufacturing; silicon thinning; smooth surface; spin-processing; spin-processing implementation; spin-processing technology; stress relief; surface damage removal; surface finish control; wafer breakage; wafer scrap; wafer strength; wafer strength characteristics; wafer strength enhancement; wafer thickness; wafer thinning; wafer warpage; wet chemical etching; wet chemical spin-processing; Assembly; Chemical processes; Chemical technology; Etching; Rough surfaces; Semiconductor device manufacture; Silicon; Stress; Surface resistance; Surface roughness;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Manufacturing Technology Symposium, 2000. Twenty-Sixth IEEE/CPMT International
Conference_Location
Santa Clara, CA
ISSN
1089-8190
Print_ISBN
0-7803-6482-1
Type
conf
DOI
10.1109/IEMT.2000.910733
Filename
910733
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