Configurable arithmetic arrays with data-driven control

Configurable digital systems offer flexibility that leads to cost reduction, performance tuning, and fault tolerance. While one can use FPGA-based methods to synthesize configurable arithmetic structures, this approach results in limited functionality and/or excessive complexity, given that off-the-shelf FPGAs are endowed with only bit-level computational capabilities. Using serial arithmetic cells can increase the ratio of resources devoted to computation (arithmetic, logic) versus communication (wiring), thereby improving per-chip performance or cost-effectiveness. When combined with pipelining, even the absolute latency can be improved. We argue that a controlled-precision digit-serial additive multiplier constitutes an ideal building block for configurable arithmetic arrays and detail our solutions for control of functionality, selection of precision, and reduction of power dissipation within such an array.