A new RNS architecture for the computation of the scaled 2D-DCT on field-programmable logic

Author

Fernández, P.G. ; Ramírez, J. ; García, A. ; Parrilla, L. ; Lloris, A.

Author_Institution

Dept. of Electr. Eng., Jaen Univ., Spain

Volume

1

fYear

2000

fDate

Oct. 29 2000-Nov. 1 2000

Firstpage

379

Abstract

This paper shows the implementation of an 8/spl times/8 scaled two-dimensional Discrete Cosine Transform processor (2D-DCT) based on the Residue Number System (RNS). The row-column decomposition technique is used and each 1D-DCT processor has been derived by the application of a previously developed scaled Fast Cosine Transform (FCT) algorithm that requires a reduced number of multiplications. Simulations of binary 2´s complement and RNS version of the scaled 2D-DCT processor using VHDL over Field-Programmable Logic (FPL) devices provide a throughput improvement for the proposed RNS-based 2D-DCT processor of up to 148% when 8-bit moduli are used. This is achieved due to the synergy between RNS and modern FPL device families.

Keywords

discrete cosine transforms; programmable logic devices; residue number systems; 8 bit; VHDL; binary two´s complement; fast cosine transform algorithm; field programmable logic; residue number system architecture; row-column decomposition; scaled two-dimensional discrete cosine transform processor; Arithmetic; Computer architecture; Discrete cosine transforms; Dynamic range; Hardware; Image coding; Matrix decomposition; Programmable logic arrays; Programmable logic devices; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-6514-3

Type

conf

DOI

10.1109/ACSSC.2000.910982

Filename

910982