• DocumentCode
    1743226
  • Title

    A new pipelined implementation of the fast Fourier transform

  • Author

    Yu, Sungwook ; Swartzlander, Earl E., Jr.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
  • Volume
    1
  • fYear
    2000
  • fDate
    Oct. 29 2000-Nov. 1 2000
  • Firstpage
    423
  • Abstract
    This paper presents a new pipelined architecture for the N/sup m/-point FFT (Fast Fourier Transform). Unlike conventional pipelined architectures, which are based on the DIT (Decimation in Time) or DIF (Decimation in Frequency) algorithms, the proposed architecture is based on a new index mapping scheme which has two levels of decomposition. As a result, the new architecture can be efficiently used to realize a pipelined implementation of the N/sup m/-point m-dimensional DFT simply by omitting some of the twiddle factor ROMs.
  • Keywords
    discrete Fourier transforms; fast Fourier transforms; pipeline processing; DFT; FFT; Fast Fourier Transform; index mapping scheme; pipelined architecture; Computer architecture; Discrete Fourier transforms; Fast Fourier transforms; Frequency; Multidimensional systems; RNA; Read only memory; Throughput; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on
  • Conference_Location
    Pacific Grove, CA, USA
  • ISSN
    1058-6393
  • Print_ISBN
    0-7803-6514-3
  • Type

    conf

  • DOI
    10.1109/ACSSC.2000.910990
  • Filename
    910990