Title :
A CAD tool for first hand CMOS circuit selection
Author :
Sun, P. ; Al-Khalili, A.J. ; Al-Khalili, D.
Author_Institution :
Concordia Univ., Montreal, Que., Canada
Abstract :
For a given Boolean expression, various CMOS circuit implementations are possible. In this paper we describe a CAD tool that aids the designer towards optimum circuit selection with first hand information on delay, area and power consumption. The program reads in a function description from SIS in BLIF format. Using factoring technique, several versions of the function are derived then a multi-level logic synthesis and minimization algorithms map each function into a circuit topology. The tool then analyzes the performance of each circuit and finds the optimum circuit topology and transistor sizing according to the given criteria supplied as weights (constants) to the program
Keywords :
CMOS logic circuits; circuit CAD; circuit simulation; integrated circuit design; logic CAD; minimisation; network topology; BLIF format; Boolean expression; CAD; CMOS circuit selection; circuit simulation; constants; factoring technique; invertor; minimization algorithms; multi-level logic synthesis; optimum circuit selection; optimum circuit topology; power consumption; transistor sizing; Analytical models; Circuit synthesis; Circuit topology; Delay; Design automation; Inverters; Logic circuits; MOSFETs; SPICE; Semiconductor device modeling;
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
DOI :
10.1109/ICECS.2000.911509
