DocumentCode :
1743381
Title :
Formalising VERILOG
Author :
Jifeng, He ; Huibiao, Zhu
Author_Institution :
Int. Inst. for Software Technol., United Nations Univ., Macau
Volume :
1
fYear :
2000
fDate :
2000
Firstpage :
412
Abstract :
This paper defines a non-trivial subset of VERILOG using a Plotkin-style operational semantics. We discuss the algebraic properties of programs based on the notion of bisimulation
Keywords :
hardware description languages; programming language semantics; Plotkin-style operational semantics; VERILOG; algebraic properties; bisimulation; Computational modeling; Computer errors; Computer languages; Concurrent computing; Data structures; Hardware design languages; Libraries; Silicon; Time sharing computer systems; Very high speed integrated circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
Type :
conf
DOI :
10.1109/ICECS.2000.911568
Filename :
911568
Link To Document :
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