Title :
A test pattern generation unit for memory NPSF built-in self test
Author :
Chrisanthopoulos, A. ; Kamoulakos, G. ; Tsiatouhas, Y. ; Arpoyanni, A.
Author_Institution :
Adv. Silicon Solutions Div., Integrated Syst. Dev. S.A., Athens, Greece
Abstract :
In this paper we present the design of a deterministic Test Pattern Generation (TPG) unit which can be exploited in a Built-In Self-Test (BIST) scheme for memory Neighborhood Pattern Sensitive Fault (NPSF) testing. The proposed TPG generates the required 5-bit Eulerian sequence that is needed for memory Type-1 NPSF testing
Keywords :
automatic test pattern generation; built-in self test; integrated circuit testing; integrated memory circuits; sequences; ATPG; BIST scheme; Eulerian sequence; TPG unit; deep submicron memories; deterministic test pattern generation; memory NPSF built-in self test; neighborhood pattern sensitive fault testing; test pattern generation unit; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Informatics; Life estimation; Signal processing; Silicon; System testing; Test pattern generators;
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
DOI :
10.1109/ICECS.2000.911571
