A programmable FIR filter using serial-in-time multiplication and canonic signed digit coefficients

In this paper, the structure of a serial-in-time multiplier-accumulator realized with binary weighted shifts (BWSMAC) is described. The multiplier-accumulator structure is then used to realize a programmable FIR filter. This filter structure makes it possible to trade the complexity of the filter coefficients to the power dissipation without leaving any “dummy” or quiet hardware in the filter tap. The highest sampling rate used in the filter depends on the complexity of the filter coefficients. The operation frequency of individual filter taps can be selected to be the lowest possible leading to on-demand power dissipation. This structure gives almost the same programmability as filters realized with multipliers. However, one coefficient can be realized with only one adder, a register stage and some multiplexers leading to an extremely simple filter structure