A tool for two´s complement, bit-level, fixed-point simulation of digital filters

Author

Abdel-Raheem, Esam ; El-Guibaly, Fayez

Author_Institution

Dept. of Electron. & Commun. Eng., Ain Shams Univ., Cairo, Egypt

Volume

1

fYear

2000

fDate

2000

Firstpage

587

Abstract

A tool for software implementation of digital filter architectures is presented. The implementation is based on fixed-point arithmetic using bit-level logic modules to reflect the actual hardware. The tool can be used in academia as well as for hardware verification. Several finite-duration impulse response (FIR) and infinite duration impulse response (IIR) filter architectures are implemented to illustrate the capabilities of the tool

Keywords

FIR filters; IIR filters; circuit simulation; digital filters; fixed point arithmetic; software tools; FIR filter architectures; IIR filter architectures; bit-level logic modules; digital filters; finite-duration impulse response filter; fixed-point arithmetic; hardware verification; infinite duration impulse response filter; software implementation; software tool; two´s complement bit-level fixed-point simulation; Clocks; Computer architecture; Digital filters; Filtering algorithms; Finite impulse response filter; Fixed-point arithmetic; Hardware; IIR filters; Quantization; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on

Conference_Location

Jounieh

Print_ISBN

0-7803-6542-9

Type

conf

DOI

10.1109/ICECS.2000.911608

Filename

911608