Title :
An effective output-oriented algorithm for low power multipartition architecture
Author :
Ruan, Shanq-Jang ; Lin, Jen-Chiun ; Chen, Po-Hung ; Lai, Feipei ; Tsai, Kun-Lin ; Yu, Chung-Wei
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
Circuit partition for low power is a useful technique which reduces power dissipation by confining the switching activity to a subcircuit. In this paper, we propose an effective output-oriented partition algorithm for low power combinational logic circuits. We discuss the relationship between power dissipation, area complexity and input/output behavior of the combinational circuit rather than inspect its logic function. Experimental results show that our algorithm can obtain sizable power saving over a wide range of MCNC benchmarks
Keywords :
combinational circuits; logic CAD; logic partitioning; low-power electronics; MCNC benchmarks; Shannon expansion; area complexity; circuit partition; input/output behavior; low power combinational logic circuits; low power multipartition architecture; output-oriented algorithm; power dissipation; power saving; switching activity confinement; Combinational circuits; Computer architecture; Entropy; Input variables; Latches; Logic circuits; Partitioning algorithms; Power dissipation; Senior members; Switching circuits;
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
DOI :
10.1109/ICECS.2000.911613