DocumentCode
1743993
Title
Study and implementation of system control for the HDTV video decoder
Author
Liu, Jian ; Jiang, Jie
Author_Institution
Sch. of Electron. Inf. Eng., Tianjin Univ., China
fYear
2000
fDate
2000
Firstpage
871
Lastpage
874
Abstract
This paper presents a design and implementation of system control for HDTV video decoder. The principle of the system control is described in detail too. FPGA is adopted for its programmable and reconfigurable features. The system control works perfectly and steadily which ensures the perfect working of decoder and display buffer
Keywords
decoding; high definition television; reconfigurable architectures; video signal processing; FPGA; HDTV; display buffer; programmable features; reconfigurable features; system control; video decoder; Buffer storage; Computer displays; Control systems; Decoding; Design engineering; Field programmable gate arrays; HDTV; Kernel; Prototypes; TV;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location
Tianjin
Print_ISBN
0-7803-6253-5
Type
conf
DOI
10.1109/APCCAS.2000.913659
Filename
913659
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