Title :
HALOTIS: High Accuracy Logic TIming simulator with inertial and degradation delay model
Author :
Juan-Chico, J. ; Bellido, M.J. ; Acosta, A. ; Valencia, Manuel
Abstract :
This paper presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm is intended for including the inertial and degradation delay models. Simulation results are very similar to those obtained by electrical simulators, and show a higher accuracy compared to conventional delay models implemented in current logic simulators
Keywords :
circuit simulation; delay estimation; digital integrated circuits; logic simulation; timing; HALOTIS; degradation delay model; events; high accuracy logic timing simulator; inertial delay model; simulation algorithm; transitions; Accuracy; CMOS logic circuits; Circuit simulation; Degradation; Delay; Digital circuits; Discrete event simulation; Logic circuits; Semiconductor device modeling; Timing;
Conference_Titel :
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0993-2
DOI :
10.1109/DATE.2001.915065
