Title :
On the verification of synthesized designs using automatically generated transformational witnesses
Author :
Teica, Elena ; Radhakrishnan, Rajesh ; Vemuri, Ranga
Author_Institution :
Dept. of Electron. Comput. & Eng. Comput. Sci., Cincinnati Univ., OH, USA
Abstract :
Summary form only given. The authors present a new methodology for verifying the synthesized designs, and for debugging the software implementation of high-level synthesis algorithms. The methodology is based on a a set of 7 RTL transformations which are able to emulate the effect of many scheduling and resource allocation algorithms
Keywords :
formal verification; high level synthesis; processor scheduling; program debugging; resource allocation; HLS algorithm; RTL transformations; automatically generated transformational witnesses; design verification; high-level synthesis algorithms; resource allocation algorithm emulation; scheduling algorithm emulation; software implementation debugging; synthesized designs; Algorithm design and analysis; Data structures; Decision support systems; High level synthesis; Information analysis; Logic; Partitioning algorithms; Resource management; Scheduling algorithm; Software debugging;
Conference_Titel :
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0993-2
DOI :
10.1109/DATE.2001.915123
