DocumentCode
1744456
Title
An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC)
Author
Zarkesh-Ha, Payman ; Meindl, James D.
Author_Institution
Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2000
fDate
2000
Firstpage
149
Lastpage
152
Abstract
An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC) is presented using models for global signal, clock, and power supply wiring networks. Based on the models for wiring resource demand, noise limit, and bandwidth requirement, an interconnect design plane is proposed
Keywords
clocks; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; power supply circuits; GSoC; bandwidth requirement model; gigascale system-on-a-chip; global clock wiring network model; global interconnects; global power supply wiring network model; global signal wiring network model; integrated architecture; interconnect design plane; noise limit model; wiring resource demand model; Bandwidth; Clocks; Crosstalk; Power supplies; Power system interconnection; Power system modeling; Semiconductor device noise; Signal design; System-on-a-chip; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on
Conference_Location
Tehran
Print_ISBN
964-360-057-2
Type
conf
DOI
10.1109/ICM.2000.916433
Filename
916433
Link To Document