A parallel genetic approach to the gate sizing problem of VLSI integrated circuits

Author

Benkhider, S. ; Boumghar, F. ; Baba-ali, A.R.

Author_Institution

T.S. Inst., USTHB, Bab-Ezzouar, Algeria

fYear

2000

fDate

2000

Firstpage

169

Lastpage

173

Abstract

This paper describes the implementation of a software CAD (computer aided design) tool, applied to the sizing problem of standard cells in VLSI integrated circuits. Unfortunately, the sizing problem belongs to the class of NP-complete problems, and the size of VLSI circuits may be huge. As a consequence, we studied heuristic solutions in order to solve this problem. This software performs circuit timing optimization, based on an evolutionary approach. The genetic algorithm is a meta-heuristic which gives near-optimal solutions with polynomial running times

Keywords

VLSI; circuit CAD; circuit optimisation; genetic algorithms; integrated circuit design; parallel processing; software tools; timing; NP-complete problems; VLSI circuit size; VLSI circuits; VLSI integrated circuits; circuit timing optimization; computer aided design tool; gate sizing problem; genetic algorithm; heuristic solutions; meta-heuristic; near-optimal solutions; parallel genetic approach; polynomial running times; sizing problem; software CAD tool; standard cells; Circuits; Design automation; Genetic algorithms; NP-complete problem; Polynomials; Software performance; Software standards; Software tools; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on

Conference_Location

Tehran

Print_ISBN

964-360-057-2

Type

conf

DOI

10.1109/ICM.2000.916438

Filename

916438