Title :
FPGA implementation of digital filters synthesized using the frequency-response masking technique
Author :
Lim, Y.C. ; Yu, Y.J. ; Zheng, H.Q. ; Foo, S.W.
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore
Abstract :
The effective length of a filter designed using the frequency-response masking technique is very high and requires a very large number of delay elements. In this paper, we present some useful techniques for reducing the data transfer between the FPGA and external memory when the random logic are implemented using FPGA and the delay elements are implemented using external memory such as DRAM
Keywords :
delays; digital filters; field programmable gate arrays; frequency response; FPGA implementation; RAM; ROM; data transfer reduction; delay elements; digital filters; external memory; frequency-response masking technique; memory fetch reduction; random logic; Arithmetic; Delay effects; Design engineering; Digital filters; Field programmable gate arrays; Frequency synthesizers; Logic; Random access memory; Read only memory; Sampling methods;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921035
