Title :
Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding
Author :
Chang, Hao-Chieh ; Yang, Zhong-Lan ; Lian, Chung-Jr ; Chen, Liang-Gee
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents a hardware-efficient architecture of tree-depth scanning (TDS) and multiple-quantization (MQ) scheme for MPEC-4 still texture coding. By means of the novel architecture, the TDS can achieve its maximal throughput to area ratio and minimal external memory access with only one wavelet-tree size on-chip memory. Besides, MQ adopts the proposed POT (power of 2) quantization, which is proved to have very similar performance to generic (user-defined coefficients) scalar quantization, to achieve the most cost-effective hardware implementation. The prototyping chip has been implemented in a TSMC 0.35 μm CMOS technology. This architecture can handle 30 4-CIF frames per second with 5 spatial layers and 3 SNR layers scalability at 100 MHz clock frequency
Keywords :
CMOS digital integrated circuits; code standards; data compression; digital signal processing chips; high-speed integrated circuits; image coding; image processing equipment; image texture; quantisation (signal); telecommunication standards; 0.35 micron; 100 MHz; MPEG-4 still texture coding; TSMC CMOS technology; hardware-efficient architecture design; multiple quantization scheme; one wavelet-tree size onchip memory; power of two quantization; tree-depth scanning; CMOS technology; Entropy coding; Frequency; Hardware; Image coding; MPEG 4 Standard; Quantization; Throughput; Transform coding; Wavelet transforms;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921040
