Title :
A high-speed pattern decoder in MPEG-4 padding block hardware accelerator
Author :
Mo, Hyeon-Cheol ; Kim, Jong-Sun ; Kim, Lee-Sup
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
Abstract :
A new pattern decoder in a MPEG-4 padding block is proposed. Necessities have been growing for the padding block to be implemented as a dedicated hardware because padding block belongs to the critical path of the MPEG-4 encoding procedure. In the padding block, the pattern decoder is the most complicated part. Therefore, an efficient hardware design is needed for the pattern decoder. To implement it as hardware, the proposed decoder uses the modified repetitive padding algorithm. In the modified repetitive padding algorithm, the conventional three cases of Binary Alpha Block (BAB) pattern were simplified to just one case. Its regularity makes it easy for the pattern decoder to be hardware-implemented. The simulation results show that the proposed pattern decoder can be effectively used for implementing high-speed MPEG-4 padding block
Keywords :
CMOS digital integrated circuits; code standards; data compression; decoding; digital signal processing chips; high-speed integrated circuits; image coding; video coding; 0.25 micron; 2 GHz; CMOS decoder chip; MPEG-4 padding block hardware accelerator; binary alpha block pattern; efficient hardware design; high-speed pattern decoder; modified repetitive padding algorithm; Acceleration; Data structures; Decoding; Encoding; Hardware; MPEG 4 Standard; Object oriented modeling; Shape;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921041
