Parallel implementation of H.263 encoder for CIF-sized images on quad DSP system

Author

Lehtoranta, Olli ; Hamalainen, Timo ; Saarinen, Jukka

Author_Institution

Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland

Volume

2

fYear

2001

fDate

6-9 May 2001

Firstpage

209

Abstract

A parallel implementation of H.263/MPEG-4 video encoder for Common Intermediate Format (CIF, 352×288) pictures is presented. The implementation runs on Hunt Engineering´s Hepcδ DSP-carrier featuring four TMS320C6201 ICs. The experimental results show real-time encoding speed of 30 fps has been reached using configuration of a master and two slave encoding DSPs. In addition, DSP-to-DSP link requirements, image quality vs. bit rate, scalability and frame rate performance are measured and analyzed

Keywords

digital signal processing chips; parallel architectures; real-time systems; video coding; 101376 pixel; 288 pixel; 352 pixel; CIF-sized images; DSP-to-DSP link requirements; H.263 encoder; Hepcδ DSP-carrier; MPEG-4 video encoder; bit rate; frame rate performance; image quality; quad DSP system; real-time encoding speed; scalability; slave encoding DSPs; Bandwidth; Clocks; Concurrent computing; Delay; Digital signal processing; Encoding; Hardware; Scalability; Video coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921044

Filename

921044