A fast motion estimation algorithm and low-power 0.13-μm CMOS motion estimation circuits

Author

Enomoto, Tadayoshi ; Kotabe, Akira

Author_Institution

Graduate Sch. of Sci. & Eng., Chuo Univ., Tokyo, Japan

Volume

2

fYear

2001

fDate

6-9 May 2001

Firstpage

449

Abstract

To drastically reduce the power dissipation (P) of motion estimation (ME) circuits, a fast ME algorithm called the “multi-step improved breaking-off-search (M-IBOS)” has been developed. M-IBOS can improve the speed of a full search algorithm by a factor of 4 to 8.5, while achieving the same visual quality. A new 0.13-μm CMOS accumulation-type ME circuit for M-IBOS has been designed. P is reduced to 374 μW, which is 1/1754 that of the previously developed 0.6-μm CMOS Wallace-tree ME circuit

Keywords

CMOS digital integrated circuits; image processing equipment; low-power electronics; motion estimation; 0.13 micron; 374 muW; CMOS motion estimation circuits; M-IBOS; accumulation-type ME circuit; full search algorithm; low-power circuits; motion estimation algorithm; multi-step improved breaking-off-search; power dissipation; visual quality; CMOS logic circuits; Capacitance; Degradation; Frequency estimation; Logic gates; Motion estimation; Niobium; Power dissipation; Power engineering and energy; Systems engineering and theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921104

Filename

921104