Title :
A dual-rail static edge-triggered latch
Author :
Ding, Li ; Mazumder, Piizaki ; Srinivas, Nagendra
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
This paper describes a simple and compact dual-rail static edge-triggered latch (DSETL) with reduced latency over conventional static flip-flops. Power consumption of the DSETL is observed to be the lowest among high performance flip-flops. It consumes up to 51% less power than dual-rail hybrid latch-flip-flop and up to 25% less than conditional-capture flip-flop in practical circuits
Keywords :
CMOS logic circuits; flip-flops; low-power electronics; sequential circuits; dual-rail static latch; latency reduction; power consumption reduction; static edge-triggered latch; static flip-flops; Arithmetic; Circuit synthesis; Clocks; Delay; Energy consumption; Flip-flops; Latches; Pulse generation; Signal generators; Switches;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921153
