Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product

We address the need for high performance adders and the desire to minimize area within the realm of logarithmic adders with a fanout of two. The area-delay product is chosen as the metric for defining the optimal logarithmic adder. Restricting the fanout to two gives rise to log₂ N possible logarithmic adder structures, where N is the adder width. We propose a first-order model to quickly analyze the general characteristics of the area-delay product. Furthermore, we present an algorithm to construct an abstract structure for any logarithmic adder with a fanout of two. Finally, we introduce a second-order model that complements the first-order model by allowing a more detailed analysis of area and delay