Computational properties of LDI/LDD lattice filters

Author

Holmberg, Johnny ; Harnefors, Lennart ; Landernas, Krister ; Signell, Svante

Author_Institution

Dept. of Electron., Malardalen Univ., Vasteras, Sweden

Volume

2

fYear

2001

fDate

6-9 May 2001

Firstpage

685

Abstract

In this paper, a new modified LDI/LDD allpass filler is presented, which is well suited for high throughput applications. It has one multiplier and three adders in the critical loop, and can be implemented in hardware with fewer adders than, for example, wave digital allpass filters. We also propose a maximally fast scheduling of the second-order LDI/LDD allpass filter, where cyclic scheduling is used. Some results regarding implementation of the LDI/LDD lattice filter in an FPGA are presented. Bit-serial arithmetics are considered

Keywords

all-pass filters; digital arithmetic; digital filters; field programmable gate arrays; lattice filters; scheduling; FPGA implementation; LDI/LDD lattice filters; adders; bit-serial arithmetic; computational properties; cyclic scheduling; high throughput applications; maximally fast scheduling; modified LDI/LDD allpass filler; multiplier; second-order LDI/LDD allpass filter; Adders; Arithmetic; Band pass filters; Delay; Digital filters; Electronic mail; Field programmable gate arrays; Hardware; Lattices; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921163

Filename

921163