A novel multiplier recoding technique and its application to the development of a high-speed parallel online multiply-accumulate architecture

Author

Natter, Wllianm G. ; Nowrouzian, Behrouz

Author_Institution

Synthesis & Static Verification, Nortel Networks, Ottawa, Ont., Canada

Volume

2

fYear

2001

fDate

6-9 May 2001

Firstpage

713

Abstract

This paper is concerned with the development of a novel 6-digit overlapped scanning technique for the efficient recoding of signed-binary (SB) numbers in their minimally redundant base-4 representation having (-2, -1, 0, 1, 2) as their digit set. This technique permits a reduction of the number of partial products in a multiplication by a factor of two if applied to multiplier recoding (in much the same manner as the modified-Booth recoding technique), with the added advantage of being applicable to purely SB multiplication. The proposed 6-digit overlapped scanning technique is applied to the development and the subsequent FPGA hardware is translated into an architecture for parallel online purely SB MAC operation

Keywords

digital arithmetic; encoding; field programmable gate arrays; multiplying circuits; parallel architectures; 6-digit overlapped scanning technique; FPGA hardware; MAC operation; high-speed parallel architecture; minimally redundant base-4 representation; multiplier recoding technique; online multiply-accumulate architecture; partial products reduction; signed-binary multiplication; signed-binary numbers; Application software; Arithmetic; Computer architecture; Delay; Digital signal processing; Field programmable gate arrays; Hardware; Network synthesis; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921170

Filename

921170