A compact multi-chip-module implementation of a multi-precision neural network classifier

Author

Bermak, Amine ; Martinez, Dominique

Author_Institution

Sch. of Eng. & Math., Edith Cowan Univ., Perth, WA, Australia

Volume

3

fYear

2001

fDate

6-9 May 2001

Firstpage

249

Abstract

This paper describes a novel MCM digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7 μm technology

Keywords

CMOS digital integrated circuits; VLSI; multichip modules; neural chips; neural net architecture; pattern classification; reconfigurable architectures; systolic arrays; threshold logic; CMOS prototype design; MCM digital implementation; VLSI chips; arithmetic precision; decision output layer; digital synapses; multi-precision neural network classifier; parity machine; reconfigurable classifier; scalable systolic architecture; threshold logic unit; user defined topology; Application software; Artificial neural networks; CMOS technology; Electronics packaging; Network topology; Neural networks; Neurons; Prototypes; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921294

Filename

921294