Monolithic chaotic communications system

Author

Chiang, Patrick ; Dally, W. ; Lee, E.

Author_Institution

Stanford Univ., CA, USA

Volume

3

fYear

2001

fDate

6-9 May 2001

Firstpage

325

Abstract

A chaotic transmitter and a synchronized chaotic receiver have been designed in a 0.25 μm CMOS process. Both transmitter and receiver use conversions between voltage and time to implement nonlinear tent-map functions. The transmitter outputs chaotic pulse position modulated (C-PPM) data as a stream of 2.3 V p-p pulses of <1 ns duration. The chaotic receiver uses the timing information between pulses to regain the chaotic state of the transmitter. The receiver resynchronizes within five cycles in a noise-free environment if lock is lost from the transmitter. The maximum throughput is 20 Mb/s and the bit error rate (BER) is <10^-9. The transceiver is realized on a 2.5 mm×1.5 mm die and dissipates 375 mW

Keywords

CMOS integrated circuits; chaos; data communication equipment; digital radio; error statistics; integrated circuit design; mixed analogue-digital integrated circuits; pulse position modulation; synchronisation; transceivers; 0.25 micron; 2.3 V; 20 Mbit/s; 375 mW; ASIC; BER; PPM data stream; bit error rate; chaotic pulse position modulated data; chaotic transmitter; mixed-mode circuits; monolithic chaotic communications system; nonlinear tent-map functions; resynchronization; submicron CMOS process; synchronized chaotic receiver; timing information; transceiver chip; Bit error rate; CMOS process; Chaotic communication; Pulse modulation; Throughput; Timing; Transceivers; Transmitters; Voltage; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921313

Filename

921313