Title :
Digital pulse mode neural network with simple synapse multiplier
Author_Institution :
Dept. of Comput. Sci. & Intelligent Syst., Oita Univ., Japan
Abstract :
This paper proposes a new type of digital pulse mode neural network with very simple synapse multiplier. Combined with the pulse mode operation, the multiplier is implemented with a set of AND gates. The feasibility of the proposed architecture is verified by computer simulations and experiments. The results show that the proposed MNN can be realize with much less hardware resource while providing the same performance as the conventional architecture
Keywords :
logic gates; multilayer perceptrons; multiplying circuits; neural chips; AND gates; MNN; architecture; computer simulations; digital pulse mode neural network; hardware resource; synapse multiplier; Computer architecture; Computer science; Electronics packaging; Frequency; Multi-layer neural network; Neural networks; Neurons; Pulse circuits; Pulse modulation; Registers;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921374
