Noise-reducing loop in multi-bit Σ-Δ modulators

In a single-stage multi-bit Σ-Δ modulator, the implementation of the multi-bit quantizer is often area and power consuming. When the bits of the quantizer increase, the scale of the circuit may increase exponentially and soon become practically impossible. In this paper, a new architecture, the noise-reducing loop, is proposed. It employs a quantizer with only a few bits and achieves much better performance which can only be achieved by using a huge quantizer in the conventional modulators. If accompanied with the dynamic quantization algorithm, the modulator can trace the change of the input signal and achieve near optimal performance adaptively in different working conditions