A pipeline 15-b 10-Msample/s analog-to-digital converter for ADSL applications

Author

Guilherme, Jorge ; Figueiredo, P. ; Azevedo, P. ; Minderico, G. ; Leal, A. ; Vital, J. ; Franca, J.

Author_Institution

Integrated Circuits & Syst. Group, Inst. Superior Tecnico, Lisbon, Portugal

Volume

1

fYear

2001

fDate

6-9 May 2001

Firstpage

396

Abstract

This paper describes a pipeline 15-b 10 Ms/s analog-to-digital converter in a 0.35 μm digital CMOS technology, suitable for ADSL applications. The architecture is based on a 5.5-bit front-end stage with a current-steering DAC and a continuous-time residue amplification followed by a 10-bit conventional pipeline backend ADC. The linearity is determined by the matching accuracy of the unit current sources, which can be controlled by the area and overdrive voltage of transistors. At Nyquist sampling (5 MHz) the signal-to-noise-and-distortion (SNDR) is 78.6 dB. The ADC has a differential input rang of 1.1 V and dissipates 320 mW from a 3.3 V power supply

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; digital subscriber lines; pipeline processing; 0.35 micron; 1.1 V; 15 bit; 3.3 V; 320 mW; 5 MHz; 78.6 dB; ADSL applications; analog-to-digital converter; continuous-time residue amplification; current-steering DAC; digital CMOS technology; pipeline backend ADC; unit current sources; Analog-digital conversion; Bandwidth; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS technology; Calibration; Capacitors; Linearity; Pipelines; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921876

Filename

921876