Realization of a floating-point A/D converter

Author

Piper, Johan ; Yuan, Jiren

Author_Institution

Competence Center for Circuit Design, Lund Univ., Sweden

Volume

1

fYear

2001

fDate

6-9 May 2001

Firstpage

404

Abstract

A floating-point analog-to-digital converter (FP-ADC) with a linear architecture has been implemented using an amplifier network in front of a pipeline ADC. The amplifier network has outputs with binary weighted gains, each sampled separately. The signal with the proper gain is then converted in the ADC. This structure allows instant floating point exponent determination. The mismatches in the amplifier network has been analyzed and successfully reduced. A prototype FP-ADC is currently being manufactured in a 0.35 μm double-poly CMOS process. Post-layout simulations show an operating frequency in excess of 30 MS/s with 74 dB dynamic range and 8 bit resolution

Keywords

CMOS integrated circuits; analogue-digital conversion; 0.35 micron; A/D converter; amplifier network; analog-to-digital converter; binary weighted gains; double-poly CMOS process; floating point exponent determination; floating-point ADC; linear architecture; Circuit synthesis; Distortion; Dynamic range; Feedback loop; Gain control; Manufacturing processes; Pipelines; Prototypes; Signal resolution; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921878

Filename

921878