A switched-current sample and hold circuit for low frequency applications

Author

de Lira Mendes, E. ; Loumeau, Patrick ; Naviner, Jean-Fraçois

Author_Institution

Ecole Nat. Superieure des Telecommun., Paris, France

Volume

1

fYear

2001

fDate

6-9 May 2001

Firstpage

452

Abstract

A sample and hold circuit using the 0.6 μm technology for low frequency application is presented. This circuit is based on a specific memory base cell that reduces the error caused by the output conductance. It works with a 3.3 V supply voltage, offers high-resolution and low power dissipation. Simulation results presented a -77.6 dB harmonic distortion and a 1.98 mW power dissipation for a 100 μA biasing current, a 1.28 MHz sampling frequency, and a 10 kHz frequency input signal

Keywords

CMOS analogue integrated circuits; circuit simulation; flicker noise; harmonic distortion; integrated circuit noise; low-power electronics; sample and hold circuits; switched current circuits; thermal noise; transfer functions; 3.3 V; CMOS switches; differential mode; dynamic range; flicker noise; harmonic distortion; high impedance nodes; high-resolution; low frequency applications; low power dissipation; memory base cell; noise analysis; output conductance error; simulation; switched-current sample and hold circuit; thermal noise; transfer function; 1f noise; Capacitors; Circuit noise; Circuit simulation; Current mode circuits; Frequency; Low voltage; Power dissipation; Sampling methods; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921890

Filename

921890