Clock-jitter induced distortion in high speed CMOS switched-current segmented digital-to-analog converters

The design of high-speed CMOS current-steering (sometimes called switched-current) segmented DAC converters requires an optimal segmentation to balance area and performance requirements. In this paper a new design criteria is introduced based on the effects of the clock-jitter in the DAC spectral performance measured through the SFDR. The study of the clock-jitter produced both by a random process, independent of the input sequence, and by the dI/dt noise originated in the binary to thermometer decoder is presented. In this later case the clock-jitter is not independent from the input sequence and is related with the number of input bits assigned to the thermometer code segment. Simulation results providing design guidelines for selecting the proper segmentation are also given