A low-voltage triode-MOSFET four-quadrant multiplier with optimized current-efficiency

Author

De Lima, Jader A.

Author_Institution

Dept. of Electr. Eng., Univ. Estadual Paulista, Sao Paulo, Brazil

Volume

1

fYear

2001

fDate

6-9 May 2001

Firstpage

735

Abstract

A low-voltage, low-power four-quadrant analog multiplier with optimized current-efficiency is presented. Its core corresponds to a pseudodifferential cascode, gain-boosting triode-transconductor. According to a low-voltage 1.2 μm CMOS n-well process, operand differential-amplitudes are 1.0 V_pp and 0.32 V_pp for a 1.3 V supply. Common-mode voltages are properly chosen to maximize current-efficiency to 58%. Total quiescent dissipation is 260 μW. A range of PSPICE simulation supports theoretical analysis. Excellent linearity of the DC characteristic is observed. Assuming a ±0.5%-mismatch on (W/L) and V_TH, THD at full-scale is 0.93% and 1.42%, for output frequencies of 1 MHz and 10 MHz respectively

Keywords

CMOS analogue integrated circuits; analogue multipliers; circuit optimisation; low-power electronics; 1 to 10 MHz; 1.2 micron; 1.3 V; 260 muW; 58 percent; CMOS n-well process; LV triode-MOSFET four-quadrant multiplier; gain-boosting triode-transconductor; low-power operation; low-voltage multiplier; optimized current-efficiency; pseudodifferential cascode triode-transconductor; CMOS process; Circuit analysis; Degradation; Frequency; Linearity; MOSFET circuits; Neural networks; SPICE; Transconductors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921961

Filename

921961