Gate-level simulation of CMOS circuits using the IDDM model

Author

Bellido, M.J. ; Juan-Chico, J. ; De Clavijo, R. Ruiz ; Acosta, A.J. ; Valencia, M.

Author_Institution

Inst. de Microelectron. de Sevilla, Sevilla, Spain

Volume

5

fYear

2001

fDate

2001

Firstpage

483

Abstract

Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is able to take account of the propagation of arbitrarily narrow pulses. As a result, the model is ready to be applied to the simulation and verification of complex circuits. Simulation results show an accuracy similar to HSPICE and greatly improved precision over conventional delay models

Keywords

CMOS digital integrated circuits; CMOS logic circuits; circuit simulation; delay estimation; integrated circuit modelling; logic gates; timing; IDDM model; arbitrarily narrow pulse propagation; complex circuits; digital CMOS circuits; gate-level simulation; inertial/degradation delay model; logic timing simulation; timing verification; CMOS digital integrated circuits; CMOS logic circuits; CMOS process; Circuit simulation; Computational modeling; Degradation; Delay effects; Propagation delay; Semiconductor device modeling; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922090

Filename

922090