Trapezoid-to-simple polygon recomposition for resistance extraction

Author

Li, Q. ; Kang, S.M.

Author_Institution

IBM Microelectron., Fishkill, NY, USA

Volume

5

fYear

2001

fDate

2001

Firstpage

495

Abstract

Chip level resistance extraction has been carried out using heuristic functions based on layout object geometries. With prevalent hierarchical designs, layout objects on the same interconnect layer in subcells may well overlap in their parent cell. Resistance extraction based on geometrical heuristics as given by Hwang (1991) and Ladage et al. (1993), require polygons to be simple. As most layout extractors decompose polygons into trapezoids, we present a linear algorithm to recompose non-overlapping simple polygons from trapezoids. Resistance extraction can then be carried out on these simple polygons

Keywords

circuit layout CAD; computational complexity; computational geometry; electric resistance; integrated circuit layout; chip level resistance extraction; geometrical heuristics; heuristic functions; interconnect layer; layout extractor; layout object geometries; linear algorithm; nonoverlapping simple polygons; resistance extraction; trapezoid-to-simple polygon recomposition; trapezoids; Contracts; Electric resistance; Geometry; Laplace equations; Lapping; Microelectronics; Shape;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922093

Filename

922093