Title :
Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT
Author :
Yoo, Seung-Moon ; Jung, Seong-Ook ; Kang, Sung-Mo
Author_Institution :
Dept. of Electr. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
In this paper, a new test pattern generator with a 2-level LFSR and a fast pattern transferring method for the scan-based BIST structure are proposed. XOR input paths in the 2-level LFSR scheme are changed by counter outputs to generate less linear-dependent and auto-correlated test patterns for better fault coverage. Test patterns are transferred into the scan chain by using an asynchronous internal high frequency clock to reduce test time
Keywords :
automatic test pattern generation; boundary scan testing; built-in self test; fault diagnosis; logic testing; shift registers; ATPT; XOR input paths; asynchronous internal high frequency clock; asynchronous test pattern transfer; auto-correlated test patterns; counter outputs; fault coverage; high efficiency BIST scheme; pattern transferring method; scan chain; scan-based BIST structure; test pattern generator; test time; two-level LFSR; Built-in self-test; Circuit faults; Circuit testing; Costs; Counting circuits; Frequency; Hardware; Logic; System testing; Test pattern generators;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922153
