DocumentCode
1745217
Title
An 8-Bit, 100-MHz low glitch interpolation DAC
Author
Zhou, Yijun ; Yuan, Jiren
Author_Institution
Dept. of Electrsci., Lund Univ., Sweden
Volume
4
fYear
2001
fDate
6-9 May 2001
Firstpage
116
Abstract
This paper describes an 8-Bit, 100-MHz current steering CMOS low glitch interpolation digital to analog converter (DAC). It includes a 16-tap voltage controlled delay line and 8-Bit based linear interpolators, making the effective clock rate up to 1.6-GHz. With the linear interpolation, the requirement on the analog reconstruction filter is relaxed, and low glitch digital to analog conversion is achieved. The chip is fabricated with a 3.3 V, 0.35 μm digital CMOS process
Keywords
CMOS integrated circuits; delay lines; digital-analogue conversion; interpolation; 0.35 micron; 1.6 GHz; 100 MHz; 3.3 V; 8 bit; analog reconstruction filter; clock rate; current steering CMOS low-glitch DAC; linear interpolation; voltage controlled delay line; Clocks; Delay lines; Digital filters; Digital-analog conversion; Frequency; Interpolation; Low pass filters; Nonlinear filters; Voltage control; Wireless communication;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922184
Filename
922184
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