A CMOS differential logic for low-power and high-speed applications

A new logic family called charge-sharing at precharge differential logic (CSPDL) is proposed. CSPDL utilises a charge-sharing scheme during the precharge phase. In order to equally charge the internal nodes to a voltage value lower than V_DD. In this way by recycling the stored charge, the power dissipation during the precharge phase is significantly reduced. Compared to other differential logic families adopting a recycling scheme, CSPDL requires no extra biasing voltages or complicated signaling schemes. Simulations demonstrate a power reduction of 30% and a delay improvement of 57% over the conventional dynamic DCVS logic