A low-cost CMOS time interval measurement core

Author

Hsiao, Ming-Jun ; Huang, Jing-Reng ; Yang, Shao-Shen ; Chang, Ein-Yuan

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

190

Abstract

A low-cost time interval measurement circuit with 0.5 ns measurable period is implemented in 0.35 μm 2P4M CMOS technology; the architecture is based on dual-slope method. The main purpose is not only concentrated on the time-interval measurement, but also the setup/hold time measurement of registers. The resolution of the proposed work is 1/16 clock period and can be extended to higher precision. In order to improve the minimal measurable time period, a settling time canceling method is proposed to force the charging procedure operated in linear region. The offset voltage of operational amplifier is also considered. The calibration of the measured results could be done easily by digital circuits

Keywords

CMOS digital integrated circuits; application specific integrated circuits; automatic test equipment; integrated circuit measurement; integrated circuit testing; logic testing; time measurement; 0.35 micron; 0.5 ns; CMOS technology; calibration; charging procedure; dual-slope method; linear region; offset voltage; operational amplifier; settling time canceling method; setup/hold time measurement; time interval measurement core; CMOS technology; Capacitors; Clocks; Integrated circuit measurements; Logic arrays; Operational amplifiers; Resistors; Switches; System-on-a-chip; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922204

Filename

922204