Title :
Low power enhancements for parallel algorithms
Author :
Klauke, Stephaiz ; Götze, Jurgeiz
Author_Institution :
Lab. of Inf. Process., Dortmund Univ., Germany
Abstract :
In this paper we present a general approach for reducing switching activity on the algorithmic level. We concentrate on iterative algorithms that are suitable for an implementation on parallel processor arrays. The reduction is substantially reached by avoiding operations that hardly contribute to the convergence of the implemented algorithm. Our general approach is exemplified on the implementation of a specific algorithm, i.e. the eigenvalue decomposition (EVD) of a real symmetric matrix
Keywords :
eigenvalues and eigenfunctions; iterative methods; low-power electronics; matrix decomposition; parallel algorithms; systolic arrays; eigenvalue decomposition; iterative algorithm; low-power design; parallel algorithm; parallel processor array; real symmetric matrix; switching activity; systolic array; Convergence; Costs; Eigenvalues and eigenfunctions; Energy consumption; Iterative algorithms; Jacobian matrices; Matrix decomposition; Parallel algorithms; Signal processing algorithms; Symmetric matrices;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922215
